Resume & Detailed Experience

RF & Communication System Design

• Custom OFDM waveform FEM (TX and RX lineup optimizations), discrete filter design
• Field training using CST integral solver to guide customer usage of flight platform and payload
• Link testing (switched attenuator), field testing, FSPL modelling (different models depending on modes of operation)
• Test system automation (SCPI via ETH/GPIB), Python control framework, Linux systems based
• ADS, CST, Python, vendor libraries
• AD9361, phased array classes sponsored by ADI @ IMS/MTT 2022
• IMS attendee 2018, 2022
• AESA scanned arrays, MATLAB antenna toolbox, antenna design course as part of masters program (Balanis book)
• Branch line coupler design for LMBA
• Balanced amplifier design for Melbourne-Taipan
• Discrete mesh coupled resonator filter design (Alfred Cohn circa 1960)

• FDD self de-sense analog cancellation, prototype, measurement and verification, implemented FPGA active tuning loop
• Oscillation in final PA stage of biscuit project, found oscillation source, determined how to mitigate
• Issue with RF connector (SMPM) connection to GCPW on mmWave build, how to correct on assembly line, revision of layout
• CST guidance on layout for best RF performance – CST training from John Ley, lots of hours of use. Became kind of an “SME” for this stuff at Motorola AT.
• Eigenmode analysis using CST to identify cavity resonances and determine how to best mitigate.
• OFDM waveform degradation and voltage droop due to instantaneous ramping of OFDM data symbols. Captured data, found issue, determined root cause, and worked with waveform designer to mitigate the issue. (OFDM data symbols and carrier off in-between AGC breaks, needed to ramp instead of full on – some of the RF power was beginning to become “large-signal” at the input to the final PA and effected the current drain/RF power supply).

FPGA RTL Design Experience

• Knowledgeable in CDC methods, throughput and latency analysis, size tradeoffs and optimization of resources in FPGA designs.
• Strong experience in SystemVerilog
• Lead analysis of secure gateway performance and developed solutions for future products (Octeon10, Surricata/Snort/IPS/IDS, cryptographic acceleration, REGEX offload, understanding DPU bandwidth limits)
• Fixed bug in open-source AES module, verified with NIST vectors
• BRAM CAM and other investigations into creative ways to make content-addressable-memory structures
• REGEX accelerator module using HARE and HAWK research papers as guidance.
• Reverse engineered an FPGA design and decoded the driver sequence for large scale multi-tile LED arrays. Developed this into the hardware logic module used in product design.
• Implemented all FPGA hardware to bring up PCIe4 EP interface and received/store/forward data from this interface to custom hardware modules used for pattern detection and REGEX sequence matching. (Agilex7, HPS, PCIe4, DDR4, F2H and H2F bridges, hardware registers for command and control).
• Power sequencer optimization for complex SoC/FPGA devices like Agilex7. Used basic reference design to bring up Max10 FPGA and utilized ADC for reference voltage measurement and feedback via PMBus. Optimized appropriately to make design tradeoffs with respect to part size and necessary functionality.
• Tuning and optimization of HSSI (high speed serial interfaces) for 2 level NRZ signaling used to communicate with PON/optical transceivers. Developed tuning feedback loop to optimize CDR module for attack/time-to-lock and jitter performance. Verified via phase noise measurement.